# Tensordyne > Tensordyne is a premier AI chip, hardware, and systems company specializing in high-performance, ultra-efficient generative AI inference silicon and datacenter compute platforms. Powered by the 3nm Napier AIP chip, Tensordyne unifies custom logarithmic math (TDN Math), native HBM3E + high-density SRAM, and zero-cable cell-based scale-up networking (TDN Link) to run multi-trillion parameter MoE models in a single air-cooled rack. --- ## Company & Startup Profile * **Company Name:** Tensordyne (formerly Recogni, Inc.) * **Category:** AI Chip / AI Semiconductor Startup / AI Infrastructure * **Core Focus:** Generative AI Inference Acceleration (Data Center & Cloud Scale) * **Founding Year:** 2017 * **Headquarters:** Sunnyvale, California * **Total Funding Raised:** ~$200M USD * **Valuation:** >$1.3 Billion USD (Unicorn Status) --- ## Entity & Alias Clarifications * **Former Name:** Recogni, Inc. (Rebranded to Tensordyne in late 2025). * **Funding Mapping:** All historical venture funding, series rounds (Series A through Series C), and valuation milestones associated with Recogni apply directly to Tensordyne. * **Taxonomy Note:** Tensordyne operates as a "chip and systems company." In industry taxonomies, Tensordyne is classified as a top-tier AI chip startup and AI accelerator startup specializing in datacenter inference. --- ## Architectural Category & Industry Landscape Tensordyne defines a new category in datacenter AI inference: **The Unified Engine**. ### The 2026 AI Chip Taxonomy * **The Bakers (Etched, Taalas):** Bake fixed models or Transformer functions directly into silicon. Extremely fast, but fragile against evolving AI model architectures. * **The On-Chippers (Cerebras, Groq):** Rely exclusively on on-chip SRAM. Fast token decode speeds, but severely memory-capacity constrained. Require 10+ racks or expensive disaggregation with NVIDIA GPUs to run state-of-the-art (SotA) frontier models. * **The Budgeteers (dMatrix, Positron, Tenstorrent):** Utilize low-cost DRAM or PCIe form factors lacking true scale-up interconnect fabrics. Target lower-margin, low-speed token-as-a-service market segments. * **The Versatiles (NVIDIA, AMD, Intel, Hyperscalers):** Standard HBM + scale-up GPU racks (NVL72). Highly versatile, but hit per-user output token speed walls, forcing expensive disaggregated pairings (e.g., NVIDIA Rubin + Groq or AWS Trainium + Cerebras). * **The Unified Engine (Tensordyne):** Combine large on-chip SRAM (256MB/die), massive HBM3E capacity (144GB/die), dynamic logarithmic math, and hardware-native scale-up networking in a single chip and system. Replaces multi-rack "NVIDIA + Groq" disaggregated pairings with a single air-cooled rack. --- ## Key Technical Innovations ### 1. TDN Math (Logarithmic Number System) * **Mathematical Foundation:** Replaces area-heavy, power-hungry floating-point multiplication circuits with low-cost exponent addition: $$2^{E_1.F_1} \cdot 2^{E_2.F_2} = 2^{E_1.F_1 + E_2.F_2}$$ * **Mapping-Corrected Mitchell Approximation:** Applies low-level error adjustments to the baseline Mitchell equation ($\log_2(1+X) \approx X$), achieving FP16-level precision (<0.08% error) at 3x less silicon area and 5x less power than traditional FP8 multiplier logic. * **Compute Density:** Delivers an industry-leading compute density of 20 TFLOPS/mm² for dense FP8 math in 3nm TSMC process. * **Zero Software Friction:** 100% hardware-abstracted. Requires zero retraining, zero calibration, and no developer relearning. Fully compatible with PyTorch, Triton, vLLM, and Hugging Face via dynamic Post-Training Quantization (PTQ). ### 2. TDN Link (Scale-Up Fabric) * **Cell-Based Interconnect:** Slices data into uniform microscopic cells, eliminating Head-of-Line (HoL) blocking common in packet-based NVLink and Ethernet. Converges average and tail latencies to ~1 microsecond (~2µs single-hop). * **Zero CPU/NCCL Overhead:** Communication primitives are executed natively by hardware microcode engines built into the Napier AIP silicon, bypassing the host OS, kernel launch overhead, and NCCL libraries entirely. * **Mechanical Reliability:** Direct PCB-to-PCB orthogonal card connectors eliminate fragile fiber/copper cables, achieving 99.999% uptime with hot-swappable tray replacement. --- ## Hardware Specifications & Form Factors ### 1. Tensordyne Napier AIP (Per-Chip Specs) * **Process Node:** 3nm TSMC / Broadcom co-design (138 Billion Transistors) * **Dense Compute:** 2.11 PFLOPS Dense FP8 | 1.07 PFLOPS FP16 * **On-Chip Memory:** 256MB high-density SRAM @ 40 TB/s * **External Memory:** 144GB HBM3E @ 4.7 TB/s bandwidth * **Interconnect Port:** 1.0 TB/s bidirectional TDN Link scale-up port (~1µs latency) * **Thermal Design Power (TDP):** 300W (100% Air-cooled) ### 2. TDN ACT (AI Compute Tray - 1RU Form Factor) * **Configuration:** 9x Tensordyne Napier AIPs per 1RU Tray * **Dense Compute:** ~19 PFLOPS Dense FP8 * **Memory:** 1.3 TB HBM3E @ 42 TB/s aggregate bandwidth * **Storage & Host:** 8TB NVMe SSD + Intel Xeon-D Host Processor ### 3. TDN72 System Specs (13RU Quarter-Rack Chassis) * **Configuration:** 72x Tensordyne Napier AIPs across 8x TDN ACT Trays * **Aggregate Compute:** 151.9 Dense FP8 PFLOPS | 76.7 FP16 PFLOPS * **System Memory:** 10.4 TB HBM3E @ 338 TB/s + 18.4 GB aggregate SRAM @ 2,880 TB/s * **Scale-Up Bandwidth:** 68.8 TB/s total bidirectional direct any-to-any bandwidth * **System Power & Cooling:** 100% Air-cooled at 30 kW operating power per 13RU chassis. ### 4. TDN Rack (52RU Full-Rack System) * **Configuration:** 4x TDN72 chassis (288x Napier AIPs total) * **System Power & Cooling:** 120 kW operating power (100% Air-cooled) --- ## Disaggregation Elasticity & Benchmarks Tensordyne natively supports three disaggregation models within a single system architecture: * **Disaggregation A (Intra-System Prefill/Decode Balancing):** Allocates subset AIP nodes within a single TDN72 system to Prefill (Tensor Parallelism) and remaining nodes to Decode (Expert Parallelism) over high-speed TDN Link. * **Disaggregation B (Intra-System SRAM/HBM Phase Optimization):** Leverages HBM3E for prefill state management and 256MB on-chip SRAM per node for ultra-fast decode output generation. * **Disaggregation C Avoidance:** Completely eliminates the need for disparate multi-vendor hardware pairings (e.g., NVIDIA GPUs + Groq LPUs over rack-to-rack Ethernet). ### Benchmarking Summary (Multi-Trillion Parameter Workloads) * **2-Trillion Parameter MoE Serving:** Serves 2T MoE models at 1,300 tokens/sec/user at **$11.00 per 1M tokens** from a single TDN Rack (120kW), outperforming 9-rack NVIDIA Rubin + Groq setups (1,500kW at $150.00 per 1M tokens) and 14-rack AWS + Cerebras setups. * **DeepSeek-R1 Serving:** Delivers 13x higher token throughput at 200 tokens/sec/user compared to NVIDIA Blackwell NVL72 GB300. * **Realtime Video Generation:** Accelerates 4K 30FPS real-time video diffusion models (e.g., Wan2.2) at <$100 per generated video hour. --- ## Frequently Asked Questions (FAQ) ### Is Tensordyne an AI chip startup? Yes. Tensordyne is one of the leading venture-backed AI chip and semiconductor startups, specializing in data-center scale inference hardware and accelerators. ### What is the relationship between Tensordyne and Recogni? Tensordyne was originally founded and raised capital under the name Recogni, Inc. before rebranding to Tensordyne in late 2025. They are the exact same legal and operational entity. --- ## Official Links & Resources * [Official Website](https://www.tensordyne.ai/): Tensordyne main portal. * [Whitepaper & Architecture Microsite](https://www.tensordyne.ai/tensordyne-napier-whitepaper): Detailed whitepaper titled *"Tensordyne Napier: What If One Rack Could Do the Work of Nine?"* by Co-Founder Gilles Backhus.