AI Inference.
At the speed you want. And the margin you need.

Moving from development to commercial reality, Napier silicon is officially transitioning into High-Volume Manufacturing (HVM) at TSMC's world-class facilities to meet the massive, immediate demand for datacenter AI infrastructure.

We finalized the complex netlist and completed the tapeout of our highly advanced 3nm Napier chip in partnership with Broadcom and TSMC, purpose-built to handle multi-modal generative AI inference at a fraction of standard energy costs.

As breakthroughs such as DeepSeek-R1 reshaped the industry, our agile, full-stack co-design approach enabled us to capitalize on these changes in real time. Throughout 2025, we optimized silicon, systems, and software to support the unique demands of Mixture of Experts (MoE) models and agentic workloads while maximizing performance, efficiency, and scalability.

To ensure our architecture translates to elite datacenter performance, we entered a strategic technology partnership with Juniper Networks. By integrating their industry-leading scale-up networking components directly with our platform, we unlock the massive fabric scalability required for modern LLM clusters.

Recognizing that our log-math innovation yields massive efficiency advantages specifically for transformer models, we made the deliberate, level-headed decision to halt legacy vision tracks and focus 100% of our engineering on Napier — our next-generation datacenter AI inference chip.

While developing the architecture for our second-generation chip, we expanded support for transformer-based models and identified a significant opportunity in emerging generative AI workloads like GPT, Stable Diffusion, and many others. Our simulations demonstrated unmatched processing efficiency, opening a compelling new market opportunity.

We successfully shipped functional Scorpio samples to our first wave of validation customers. Our Scorpio development system with surround-view object detection ran non-stop 24/7/365 with no downtime, proving our hardware's real-world reliability and performance.

We successfully taped out our first-generation Scorpio chip with Broadcom and received fully functional 7nm silicon from TSMC. This milestone successfully validated our proprietary log-math architecture in physical hardware.

We filed our first five foundational patents for log-math-based architectures and kicked off design for Scorpio, a first-generation chip proving that logarithmic mathematics could radically accelerate AI workloads at unprecedented speed and efficiency.